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Central Processor Unit (CPU) Registers
Extended Mode Register (EMR) (SR[23–16]) and Mode Register (MR) (SR[15–8]) . These
special-purpose registers define the current system state of the processor. The bits in both
registers are affected by hardware reset, exception processing, ENDDO (end current DO
loop) instructions, RTI (return from interrupt) instructions, and TRAP instructions. In
addition, the EMR bits are affected by instructions that specify SR as their destination (for
example, DO FOREVER instructions, BRKcc instructions, and MOVEC). During
hardware reset, all EMR bits are cleared. The MR register bits are affected by DO
instructions, and instructions that directly reference the MR (for example, ANDI, ORI, or
instructions, such as MOVEC, that specify SR as the destination). During processor reset,
the interrupt mask bits are set and all other bits are cleared.
Condition Code Register (CCR) (SR[7–0]) . Defines the results of previous arithmetic
computations. The CCR bits are affected by Data Arithmetic Logic Unit (Data ALU)
operations, parallel move operations, instructions that directly reference the CCR (for
example, ORI and ANDI), and instructions that specify SR as a destination (for example,
MOVEC). Parallel move operations affect only the S and L bits of the CCR. During
processor reset, all CCR bits are cleared.
The definition of the three 8-bit registers within the SR is primarily for the purpose of
compatibility with other Motorola DSPs. Bit definitions in the following paragraphs identify the
bits within the SR and not within the subregister.
Extended Mode Register (EMR)
Mode Register (MR)
Condition Code Register (CCR)
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CP[1–0] RM SM CE
SA FV LF DM SC
S[1–0]
I[1–0]
S
L
E
U
N
Z
V
C
Reset:
1 1 0 0 0 0 0 0 0 0 0 0 0 0 1
1
0
0
0
0
0
0
0
0
Reserved bit. Read as zero; write to zero for future compatibility
Figure 4-1. Status Register (SR)
DSP56311 User’s Manual, Rev. 2
Freescale Semiconductor
4-5
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